A Mixed-Signal Successive Approximation Architecture for Energy-Efficient Fixed-Point Arithmetic in 16nm FinFET

摘要

In this work, a mixed-signal architecture, inspired from the widely-popular successive approximation analog-to-digital converter, is presented as an energy-efficient alternative to conventional digital signal processors for fixed-point arithmetic. Using a capacitor array, this architecture computes multiply-add operations as charge at the thermal noise limits. Then, using this same array along with a comparator and a successive approximation register (SAR), this charge is efficiently decoded into a digital value using a binary search. This architecture was designed in a 16nm FinFET process, and is capable of computing 8-bit multiply-add operations averagely at 6.85fJ with an efficiency of 146TOPs/W. Compared to a conventional digital implementation performing the same operation in the same process, the proposed design used 37% less energy.