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Static Phase Offset Reduction Technique for Delay Locked Loops

机译:延迟锁定环的静态相位偏移减少技术

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A new static phase offset reduction technique suitable for low bandwidth delay locked loops is proposed. Chopping, which is a well-known technique for offset reduction, can be easily applied to the phase detector. Applying it to the charge pump is non-trivial and requires complex circuitry. The proposed technique reduces the offset due to both PFD and the charge pump, without actually chopping the latter. Analysis of the proposed method shows an offset reduction at least by a factor of 2. A conventional DLL, a DLL with a chopped PFD, and the proposed DLL were designed in a 130 nm CMOS process to verify the proposed technique. Monte Carlo simulations with random process and mismatch variations show that the offset improves from 19.9 ps in the conventional technique to 1.7 ps in the proposed technique.
机译:提出了一种适用于低带宽延迟锁定环的静态相位偏移降低技术。斩波是减少偏移的一种众所周知的技术,可以很容易地应用于相位检测器。将其应用于电荷泵并非易事,并且需要复杂的电路。所提出的技术减少了由于PFD和电荷泵引起的偏移,而没有实际将其斩波。对提出的方法的分析表明,偏移量至少减少了2倍。常规DLL,具有短切PFD的DLL和提出的DLL是在130 nm CMOS工艺中设计的,以验证提出的技术。带有随机过程和失配变化的蒙特卡洛模拟表明,偏移量从传统技术的19.9 ps提高到提出的技术的1.7 ps。

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