20.6 An 80MHz-BW 31.9fJ/conv-step Filtering ΔΣ ADC with a Built-In DAC-Segmentation/ELD-Compensation 6b 960MS/s SAR-Quantizer in 28nm LP for 802.11ax Applications

摘要

The demand for modern portable smart devices is growing at an unprecedented rate, which speeds up the development of the next-generation wireless-LAN (WLAN) standard. To improve spectrum efficiency and serve more users in crowded areas while increasing maximum throughput, 802.11ax supports 1024QAM modulation under MCS11 with OFDMA technology over 160MHz RF signal bandwidth (BW160). Taking channel fading margin into account, 1024QAM requires a receiver (RX) EVM better than -40dB when supporting multi-user MIMO. To satisfy the stringent RX EVM requirement, the intrinsic dynamic range (DR) of the RX analog baseband over such a wide in-band bandwidth (BW) of 80MHz must exceed 65dB to guarantee that the noise contribution is low enough, with sufficient headroom for the large peak-to-average-power-ratio of the OFDM-based 1024QAM signal. Moreover, the potential co-existence of the LTE-U TX application in the License Assisted Access band with 5G WLAN imposes extremely strict anti-aliasing requirements on the RX analog baseband. Hence, compared with discrete-time-based ADCs, which inevitably need the aid of intensive analog filtering, the continuous-time (CT) ΔΣ modulator (DSM) is a favorable RX ADC candidate due to its inherent anti-aliasing ability. The CTDSMs [1,2] achieve high DR over wide bandwidth by clocking at multi-gigahertz sampling rates to maintain a moderate oversampling ratio (OSR) with sufficient noise-shaping ability. The overhead is tens of milliwatts (mW) of power consumption per ADC, which may account for a significant portion to the total RX power and is not efficient enough for portable devices. This work presents a power-efficient 802.11ax RX analog baseband realized by a single filtering ΔΣ ADC [3] that uses a 6b 960MS/s SAR-quantizer combined with both low-latency DAC-segmentation (LLDS) functionality and excess-loop delay compensation (ELDC) [4]. While the prototype operates under an extremely low OSR of 6×, it achieves SNDR/DR of 64.9dB/68dB over an 80MHz BW with a total power consumption of 7.33mW in 28nm low-power (LP) CMOS. Meanwhile, an additionally embedded 12dB PGA gain range and a peaking-free signal transfer function (STF) make this work even more attractive for RX analog baseband applications.