首页> 外文会议>IEEE International Solid- State Circuits Conference >8.5 A Fully Integrated Voltage Regulator in 14nm CMOS with Package-Embedded Air-Core Inductor Featuring Self-Trimmed, Digitally Controlled Variable On-Time Discontinuous Conduction Mode Operation
【24h】

8.5 A Fully Integrated Voltage Regulator in 14nm CMOS with Package-Embedded Air-Core Inductor Featuring Self-Trimmed, Digitally Controlled Variable On-Time Discontinuous Conduction Mode Operation

机译:8.5 14nm CMOS的全集成稳压器,带封装嵌入式空芯电感器,具有自调整,数字控制的可变导通时间不连续导通模式操作

获取原文

摘要

Fully Integrated Voltage Regulators (FIVR) with package-embedded air-core inductors [1] or on-die solenoid inductors with planar magnetic core [2] promise efficient power delivery and fine-grain wide-range DVFS in complex SoCs while providing fast transient response. The FIVR must provide high conversion efficiency across a wide operating range of output voltages and load currents, including light to medium loads, to maximize the overall energy efficiency of the SoC across different power states. Phase shedding and switch scaling have been used for high-frequency FIVR designs with pulse-width modulation (PWM) control in continuous conduction mode (CCM) to maintain high efficiency for large load currents [1-5], and pulse-frequency modulation (PFM) and hysteretic control have been used to achieve high efficiency across light to medium loads [3-5]. In this paper, we present an FIVR in 14nm CMOS with a 2.5nH air-core inductor embedded in an ultrathin coreless package (200μm thick) (Fig. 8.5.7), featuring self-trimmed, soft-switched and digitally controlled variable ON-time DCM operation up to 70MHz to achieve high conversion efficiencies across light to medium load currents ranging from 5mA to 500mA and wide 0.7-1.2V output voltage range. The FIVR uses a cascoded thin-gate powertrain (Fig. 8.5.1) to support input voltages up to 2Vmax with the cascode bias rail set at Vin/2 which consumes <;1uA at light load. A small thick-gate device is connected across the inductor to dampen oscillations when the power stage is in a high-impedance state. The output voltage is monitored by a comparator with sub-ns response time which triggers an inductor current pulse when the output drops below the reference voltage. A resistor divider with a feedforward capacitor is used to achieve fast response time.
机译:具有封装嵌入式空心电感器的全集成稳压器(FIVR)[1]或具有平面磁芯的片上螺线管电感器[2]保证了复杂SoC中的有效功率传输和细粒度宽范围DVFS,同时提供了快速瞬态回复。 FIVR必须在广泛的输出电压和负载电流(包括轻负载到中负载)的宽工作范围内提供高转换效率,以在不同功率状态下最大化SoC的整体能效。相位脱落和开关定标已用于具有连续传导模式(CCM)的脉宽调制(PWM)控制的高频FIVR设计,以在大负载电流下保持高效率[1-5],而脉冲频率调制( PFM和磁滞控制已用于在轻载至中载时实现高效率[3-5]。在本文中,我们提出了一种14nm CMOS的FIVR,其2.5nH空心电感器嵌入超薄无芯封装(厚度为200μm)中(图8.5.7),具有自调整,软开关和数字控制的可变导通功能。 DCM运行时间高达70MHz,可在轻载至中等负载电流(5mA至500mA)和0.7-1.2V宽输出电压范围内实现高转换效率。 FIVR使用级联的薄栅极动力总成(图8.5.1)来支持高达2Vmax的输入电压,并且级联偏置电压轨设置为V。 位于 / 2,在轻负载下消耗<; 1uA。当功率级处于高阻抗状态时,一个较小的厚栅极器件跨接在电感器上,以抑制振荡。比较器监视输出电压,该比较器的响应时间为ns纳秒,当输出降至参考电压以下时,触发一个电感器电流脉冲。带前馈电容器的电阻分压器用于实现快速响应时间。

著录项

相似文献

  • 外文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号