Design of Area Effective Full Adder Using Gate Diffusion Input Logic

摘要

This paper presents a new technique for designing of full adder by usingGDIcell. In existing CMOS Logic source and substrate terminals of P-type and N-type Metal Oxide Semiconductors are always connected to supply voltage VDD and GND respectively. In the event of GDI both the sources and relating substrates of transistors are not associated with supply and it very well may be arbitrarily one-sided. The proposed work uses a smaller number of transistors, less complexityand consumes less silicon area (chip area) of Logic circuits. Full adder is designed, implemented and simulated using CMOS Transmission gate (TG). Pass transistor logic(PTL) along with TG and Gate Diffusion Input (GDI) technique by comparing no. of transistors used in three designs. GDI technique uses 10 transistors for design of full adder. Tanner EDA tool version 3.1 is used for schematic capture and simulation of full adder circuits.