Prototyping of Dual Master I~2C Bus Controller

摘要

The Inter - Integrated Circuit bus commonly called as I~2C (I squared C) or I2C bus is a serial bus invented by Philips Semiconductors during early 80's for interconnecting integrated circuits. It consists of only two active wires called SDA and SCL. In this paper, the design and implementation of a dual master - dual slave I~2C bus controller is presented. The bus controller design is implemented using VHDL based on Finite State Machine (FSM). Here, EEPROM 24C07 and 24C08 is used as the slave devices for the dual masters for performing reading and writing operations. This design is simulated using ModelSim 6.2b and is synthesized in Xilinx ISE Design Suite 14.2. The hardware implementation of the I~2C protocol is done using Spartan 3A FPGA.