An Efficient Booth Multiplier Using Probabilistic Approach

摘要

In VLSI Design, low power reduction is achieved by mainly reducing the power. At present, low power designs are predominant in VLSI due to many reasons. The main focus is to reduce the heat in the device. From the basic mathematical equations of power, reduction of power can be done by either decreasing clock, decreasing voltage or decreasing load. The option of reducing power can be done by reducing voltage as clock should be maintained for faster systems. Power reduction can be done at various levels like architecture, logic and transistor. Reduction of power and area can be done by sacrificing one factor to achieve the other. In this work, a booth multiplier is designed based on probabilistic approach. In the truncation part of partial products a probabilistic estimation bias circuit is introduced. Ripple Carry Adder (RCA) was replaced withCarry Look Ahead (CLA) adder in the implementation. Simulations were carried out using Synopsys Design Compiler for saed 90nm technology. 9.7% area reduction and 3.9^{%power reduction was reported for L=8 and L=10 when compared with existing work.}