An Efficient Implementation of LDPC Decoders on ARM Processors

摘要

In this paper, we present an ARM based decoder for Low Density Parity Check (LDPC) codes. To maximize the efficiency of the parallel execution and fully utilize the ARM processors' capacity, instruction-level parallelism optimizations are applied. Compression storage and efficient data prefetching optimizing methods are used to enhance the memory cache efficiency. The experiments are carried out on NVIDIA Jetson K1 platform. Our decoder can achieve 1.85 times speed up compared with the related work. And the decoder has better energy efficiency comparing to the decoders on x86-CPU and GPU.