RECache: ROM-Embedded 8-Transistor SRAM Caches for Efficient Neural Computing

摘要

One of the fast ways of evaluating complex math tables, transcendental functions, high-order polynomials etc. is by storing them in read-only memories (ROMs). However, storing large dedicated ROMs on-chip is not feasible as they incur large area overhead. Moreover, that part of the chip lies waste when ROMs are not in use. To that effect, we show at least three proposals to embed ROMs into on-chip caches using standard 8-transistor static random access memories (SRAMs). Just by adding an extra word-line (WL) or a source-line (SL), the same bit-cell can store a RAM bit, as well as a ROM bit, while maintaining the performance and area-efficiency of standard SRAMs. Moreover, due to the decoupled read/write port of the 8T-SRAMs, RAM data is not destroyed during ROM accesses, unlike prior works. We demonstrate the effectiveness of using such ROM-Embedded RAMs as caches (RECache). An improvement of up-to 19.4× in cache performance was achieved by using RECache under `ROM-intensive' workloads. Further, we expand the scope of RECache, and demonstrate its applicability in specialized neural hardware. Taking an example of spiking neural network (SNN) acceleration, an energy improvement of 1.7× and iso-area performance improvement of 1.9 × was achieved with RECache, compared to standard SRAM caches.