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Failure Mechanism of High Via Resistance Induced by Fluorine and Moisture

机译:氟和水分引起的高通孔电阻失效机理

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High Via resistance for borderless Via design was detected at PCM E-test step during wafer fabrication. The high via resistance wafers were sent for TEM and EDX analysis to determine the failure root cause. From the TEM images, a layer of non-conductive material is seen at the Via hole bottom. EDX analysis and probe spectrum analysis confirmed the foreign material is Al-F-O compound. A Design of Experiment (DOE) was carried out to determine the dominant factor contributing to the formation of the Al-F-O material after post Via etch clean.
机译:在晶圆制造过程中的PCM E测试步骤中检测到无边界过孔设计的高过孔电阻。将高通孔电阻晶片发送到TEM和EDX分析,以确定故障的根本原因。从TEM图像中,在通孔底部可以看到一层非导电材料。 EDX分析和探针光谱分析证实异物为Al-F-O化合物。进行了实验设计(DOE),以确定在后通孔蚀刻清洁后有助于Al-F-O材料形成的主要因素。

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