Characterization of Clock Buffers for On-Chip Inter-Circuit Communication in Xilinx FPGAs

摘要

Resource underutilization can occur in FPGAs if there is not enough routing resource to connect circuit elements in a region of the chip area. To alleviate this, we have proposed the use of clock buffers for on-chip data routing. Moreover, dynamism in communication for reliability is facilitated by using clock buffers for communication. This is because the clock routing network is independent of the general interconnect. In this paper, we present different configurations of the clock buffers in a Xilinx 7 series FPGA and characterize them based on the achievable speed of communication.