A New FPGA Implementation of a Time-to-Digital Converter Supporting Run-Time Estimation of Operating Condition Variation

摘要

A Time-to-Digital Converter (TDC) is widely used in applications that need to measure the time interval between events. Previous designs based on a feedback loop and an extended delay line suffers from poor accuracy caused by Process, Voltage, and Temperature (PVT) variations of the feedback path. This paper proposes a novel design of a synthesizable TDC that can estimate the operating event at run-time. The proposed TDC includes a ring oscillator of which oscillation period is measured at run-time to detect any change of operating event. The proposed TDC is implemented by using Xilinx Spartan-6 LX9 FPGA with 50MHz oscillator and it achieves about 19ps resolution. For 3ns time interval, the TDC detects it as 2.989ns on average with the standard deviation of about 148ps at 70°C.