A −236.3dB FoM sub-sampling low-jitter supply-robust ring-oscillator PLL for clocking applications with feed-forward noise-cancellation

摘要

A 2-2.8GHz 65nm CMOS ring oscillator PLL occupies an active area of 0.022mm^{2, consumes 5.86mW and achieves a 633fs RMS jitter at 2.36 GHz and an FOM_jitterof -236.3dB. It implements a low-overhead feed-forward phase and supply-noise cancellation scheme by leveraging the noise extraction inherently done by the sub-sampling phase detector. Cancellation reduces the jitter by 1.4x, the phase noise by 10.2dB to -123.5dBc/Hz at a 300KHz offset, and the ring oscillator supply sensitivity by 19.5dB for a 1mV_p-p100KHz supply noise tone.}