This paper presents a gate-leakage-based timer using an amplifier-less replica-bias switching technique that can realize stable and low-voltage operation with logic circuits based architecture. To generate stable oscillation frequency in low power operation, the topology that discharges the pre-charged capacitor via a gate leaking MOS capacitor with low-leakage switch is employed. The proposed amplifier-less replica-bias switching technique enables the low-voltage operation of the timer by tracking the discharging node of the capacitor and minimizing the leakages through the switch without analog circuits. The native NMOS header is implemented to reduce supply sensitivity of the timer. The test chip fabricated in 55-nm deeply depleted channel (DDC) CMOS technology achieves an energy efficiency of 25 pJ/cycle at a supply voltage of 350 mV with a body bias in a 0.0022 mm2 area, and 200-ppm Allan deviation floor.
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机译：本文提出了一种基于栅极泄漏的定时器，该定时器采用了无放大器的复制偏置切换技术，该技术可利用基于逻辑电路的架构实现稳定且低电压的操作。为了在低功率操作中产生稳定的振荡频率，采用了通过具有低泄漏开关的栅极泄漏MOS电容器使预充电电容器放电的拓扑。所提出的无放大器的复制偏置开关技术通过跟踪电容器的放电节点并通过无模拟电路的开关将泄漏降至最低，从而实现了定时器的低压操作。实施本机NMOS标头可降低计时器的电源灵敏度。采用55纳米深耗尽沟道（DDC）CMOS技术制造的测试芯片，在350 mV的电源电压下，体偏置在0.0022 mm 2 范围内，能效为25 pJ /周。和200 ppm Allan偏差底限。
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