A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation

摘要

Frequency-modulated continuous-wave (FMCW) radars with high resolution require the generation of low-phase-noise, low-spurs, and highly linear chirp signals with large peak-to-peak value (chirp bandwidth) and a short period of the modulation signal [1]. In radar systems, the spot phase noise of the chirp generator is converted to the intermediate frequency of the receiver making it difficult to detect two close targets, while spurs cause the detection of false targets. For those reasons, medium-range radar applications in the 77-to-81GHz band typically specify spot phase noise lower than -90dBc/Hz at 1MHz offset and spur level below -50dBc. Unlike triangular chirps, saw-tooth chirps allow for a reduced dead time for range detection. However, any practical modulator needs a finite time (idle time) to make a large frequency jump at the end of the saw-tooth, and this limits the duty cycle of the saw-tooth. For instance, a fast saw-tooth chirp with 200kHz rate and 95% duty cycle leaves the idle time of only 250ns. Fractional-N PLLs can be used as chirp modulators. Unfortunately, low phase noise and spur levels require a narrow PLL bandwidth, while short idle time demands for a wide one. The two-point injection of the modulation signal, both from the modulus control of the divider and the tuning input of the voltage-controlled oscillator (VCO), is a known method to simultaneously achieve a narrow PLL bandwidth and fast modulation. However, even in that scheme, a frequency modulation error is mainly limited by gain mismatch between the two injection paths and by the linearity of the VCO [2]. In this work, a 20-to-24GHz digital bang-bang PLL, which uses the two-point modulation scheme to generate triangular and saw-tooth chirp signals, is presented. Unlike previous works [1-4], this architecture is able to generate fast saw-tooth chirps with the slope up to 173MHz/js, the idle time below 200ns, and the rms frequency error of better than 0.06%. The gain mismatch between the two modulation paths are automatically calibrated by a digital algorithm [5], and the input of the digitally controlled oscillator (DCO) is pre-distorted via an automatic background correction scheme, which compensates for the DCO nonlinearity.