FinFETanowire design for 5nm/3nm technology nodes: Channel cladding and introducing a “bottleneck” shape to remove performance bottleneck

摘要

Transition from planar MOSFETs to FinFETs enabled scaling beyond 28nm node. At 5nm/3nm design rules, a transition from FinFETs to nanowires has to be evaluated. We explore with rigorous NEGF (Non-Equilibrium Green's Functions) and sub-band Boltzmann transport models the impact of nanowire shape and SiGe/Si cladding layers on its performance and variability. Outside of the nanowire channel, a “bottleneck” shape of the source/drain extensions can either boost or ruin the performance, requiring NEGF-driven meticulous shape engineering.