III–V/Ge MOSFETs and TFETs for ultra-low power logic LSIs

摘要

CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport properties. In addition, Tunnel FETs (TFETs) using Ge/III-V materials are regarded as one of the most important steep slope devices for the ultra-low power applications. In this presentation, we address the device and process technologies of Ge/III-V MOSFETs and TFETs on the Si CMOS platform. Viable technologies of MOS channel, gate stack, source/drain and tunnel junction formation are introduced for satisfying the device requirements.