Effective DC fault models and testing approach for open defects in analog circuits

摘要

The detection level of defects in today's mixed-signal ICs lags behind the extremely high demand of industries such as automotive. This is mainly because analog blocks in these ICs have high test escape rates as a result of the typical testing based on the performance specifications. Defect-oriented techniques have been proposed to solve the problem of this poor fault coverage for analog circuits. Their effectiveness in practice is however still limited due to the inadequate fault models used to represent physical failures. This paper presents a new open-gate DC fault model. Experimental results on fabricated test circuits in 0.35μm BCD technology are used to validate the proposed fault model and the commonly used high-value-resistance model. Finally, a new testing approach to detect the corresponding open defects in analog circuits is discussed, which is based on forcing the transistors outside their designed operation region.