Efficient Emulation of Floating-Point Arithmetic on Fixed-Point SIMD Processors

摘要

In this paper, a software floating-point emulation library for fixed-point SIMD processors is proposed. The single instruction multiple data (SIMD) mechanism of those processors is exploited in this work to efficiently emulate fast software floating-point operations. The key feature of this approach is the independent processing of the significand and the exponent, stored in different sized subwords of one SIMD word. Additional processing performance is obtained by computing multiple floating-point operations in parallel using one SIMD instruction. Compared to related work, no additional hardware overhead is required to speed up the software emulation of floating-point arithmetic. An evaluation of fixed-and floating-point signal processing algorithms, implemented on a fixed-point VLIW-SIMD processor, shows the differences in performance, precision, and code size.