Multistage test data compression technique for VLSI circuits

摘要

A hybrid test data compression method is presented which is targeted at minimizing the volume of test data, which reduces memory requirements for test data and also time required to test the entire data. The compression scheme is so called hybrid as it combines a transform along with the encoding scheme. In the proposed approach, encoding schemes such as Frequency Directed Run length encoding and Shannon Fano encoding schemes are applied on the transformed data. The proposed scheme is applied on ISCAS'85, ISCAS'89 and ITC'99 benchmark circuits and compared in terms of their compression ratio.