A transient enhanced external capacitor-less LDO with a CMOS only sub-bandgap voltage reference

摘要

This paper presents an external capacitor-less low-dropout(LDO) regulator with a voltage spike detection circuit for the enhanced transition response and with a CMOS only sub-bandgap voltage reference(BGR) operated in subthreshold region. CMOS sub-BGR adopted a weighted Vgs structure and a body bias technique for reducing the variations from process, voltage and temperature (PVT). The proposed LDO achieved the PSRR of -96dB at DC and -34dB at 1MHz by using 3-stage configuration. The proposed LDO operates with the reference voltage of 283mV from the Sub-BGR and provides the output voltage of 1.5V. Simulated results shows that overshoot and undershoot of output voltage were reduced to 62mV and 56mV respectively when the load current changes from 0 to 50mA. Total power consumption was 60μA and the chip area was 0.03358mm2 with 0.18μm CMOS process.