Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

摘要

We report a comprehensive evaluation of junctionless (JL) vs. conventional inversion-mode (IM) gate-all-around (GAA) nanowire FETs (NWFETs) with the same lateral (L) configuration. Lower IOFF values and excellent electrostatics can be obtained with optimized NW doping for a given JL NW size (WNW≤25nm, HNW~22nm), with increased doping enabling ION improvement without IOFF penalty for WNW ≤10nm. These devices also appear as a viable option for analog/RF, showing similar speed and voltage gain, and reduced LF noise as compared to IM NWFETs. VT mismatch performance shows higher AVT with increased NW doping for JL NMOS, with less impact seen for PMOS and at smaller NWs. The JL concept is also demonstrated in vertical (V) GAA-NWFETs with in-situ doped Si epi NW pillars (dNW≥20-30nm), integrated on the same 300mm Si platform as lateral devices. Low IOFF, IG, and good electrostatics are achieved over a wide range of VNW arrays. Lastly, a novel SRAM design is proposed, taking advantage of the JL process simplicity, by vertically stacking two VNWFETs (n or p/p) to reduce SRAM area per bit by 39%.