首页> 外文会议>IEEE Symposium on VLSI Technology >Vertical Heterojunction Ge_0.92Sn_0.08/Ge GAA Nanowire pMOSFETs: Low SS of 67 mV/dec, Small DIBL of 24 mV/V and Highest G_m,ext of 870 μ S/μ m
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Vertical Heterojunction Ge_0.92Sn_0.08/Ge GAA Nanowire pMOSFETs: Low SS of 67 mV/dec, Small DIBL of 24 mV/V and Highest G_m,ext of 870 μ S/μ m

机译:垂直异质结GE_0.92SN_0.08 / GE GAA纳米线PMOSFET:低SS为67 MV / DEC,小DIBL 24 MV / V和最高G_M,EXT870μS/μM

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We demonstrate high performance vertical heterojunction Ge0.92Sn0.08/Ge gate-all-around (GAA) nanowire (NW) pMOSFETs enabled by a top-down approach, a self-limiting digital etching and NiGeSn metallization. Thanks to the GAA NW geometry and EOT scaling, low SS of 67 m V /dec, small DIBL of 24 m V/ V, and a high $mathrm{I}_{mathrm{ON}}/mathrm{I}_{mathrm{OFF}}$ ratio of ~ 106 are achieved in the smallest NW device with a diameter down to 25 nm. Furthermore, record high $mathrm{G}_{mathrm{m},mathrm{ext}}$ of ~870 $mu mathrm{S}/mu mathrm{m}$ and the best quality factor $mathrm{Q}=mathrm{G}_{mathrm{m},mathrm{ext}}mathrm{SS}_{mathrm{sat}}$ of 9.1 are obtained for all reported GeSn-based pFETs.
机译:我们展示了高性能垂直异质结Ge0.92sn0.08 / ge门 - 全栅(Gaa)纳米线(Gaa)纳米线(GaW)PMOSFET通过自上而下的方法,自限制数字蚀刻和Nigesn金属化。由于Gaa NW几何和EOT缩放,低SS为67米V / DEC,小DIBL 24 M V / V,高 $ mathrm {i} _ { mathrm {上}} / mathrm {i} _ { mathrm {off}} $ 比率〜10 6 在最小的NW器件中实现,直径降至25nm。此外,记录高 $ mathrm {g} _ { mathrm {m}, mathrm {ext}} $ 〜870 $ mu mathrm {s } / mu mathrm {m} $ 和最好的品质因素 $ mathrm {q} = mathrm {g} _ { mathrm {m}, mathrm {ext}} mathrm {ss} _ { mathrm {sat}} $ 获得9.1的所有报告的基于GESN的PFET。

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