COTS Multicore Processors in Avionics Systems: Challenges and Solutions

摘要

In this paper we discuss the challenges introduced by the shared memory hierarchy of multicore processors to the predictability of real-time system. In particular, the shared memory induces unpredictable time delays that can make real-time tasks miss their deadlines. We then present the techniques we developed to create cache and memory partitions using page coloring techniques that minimizes the memory delays and make them predictable. To allocate these partitions we present a coordinated private partition allocation algorithm. Given that the number of partitions that is possible to create on COTS hardware can be small we also present a timing analysis for shared bank partitions. These solutions are finally evaluated on a small avionics model problem using a ball-following control algorithm. This problem allows us to verify the effectiveness of our partitioning mechanisms as they are able to guarantee the timing of the algorithm that cannot be preserved without it.