Variation improvement for manufacturable FINFET technology

摘要

This works examines the sources of electrical variation for FinFET technology based on silicon data from 90nm contacted poly pitch, dual-epitaxy, and RMG (replacement metal gate) transistor. A simple statistical model is used to predict electrical variation based on physical variation that can be measured much earlier in the processing flow. The model is also used to define specification and control limits for physical variation to support the electrical variation specified in SPICE models. Gate stack, Junction, and Gate height variation are identified to be the key contributors to threshold voltage variation for FinFET technology. A case study is also presented on controlling gate height to the desired specification limits by improving across chip, within wafer, wafer to wafer, and lot to lot variation at multiple process steps.