A 25-Gb/s FIR equalizer based on highly linear all-pass delay-line stages in 28-nm LP CMOS

摘要

FIR filters are attractive to enhance the equalization performances of high speed wireline receivers, providing high flexibility to match the channel frequency response and compatibility with simple adaptation techniques. This paper presents a 25-Gb/s 4-tap FIR equalizer in 28-nm LP CMOS. To keep high SNR and not compromise equalization performances, a new all-pass stage is proposed to realize a delay line accommodating large input signal amplitude. The chip draws 25 mA from 1V supply and measurements with 900 mV input signal prove equalization of a 20-dB loss channel with 50% horizontal eye opening at BER=10. Experimental results compare favorably against state of the art.