Design of low density parity check decoder using Min-Sum algorithm

摘要

Low density parity check (LDPC) code has received more attention due to their excellent error correcting performance capabilities. An LDPC code can be decoded using iterative method like the sum-product algorithm and the Min-Sum algorithm based on its Tanner graph. In this paper, fully parallel architecture has been designed for LDPC decoder using Min-Sum algorithm. This decoder modeled in Verilog synthesized and performed place and route for design using Xilinx 13.1.