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An embedded probabilistic extraction unit for on-chip jitter measurements

机译:用于片上抖动测量的嵌入式概率提取单元

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As circuits become increasingly complex and testing time continues to increase, it is becoming more and more important to use built-in self-test techniques to ensure that the circuit is working according to its data sheet specifications. This paper presents an embedded test instrument in an IBM 130 nm CMOS technology, which allows for quick and easy probabilistic test evaluation of the bit-error ratio of a device-under-test.
机译:随着电路变得越来越复杂并且测试时间不断增加,使用内置的自测技术来确保电路根据其数据手册规范工作变得越来越重要。本文介绍了一种采用IBM 130 nm CMOS技术的嵌入式测试仪器,该仪器可对被测设备的误码率进行快速,轻松的概率测试评估。

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