Analysis implementation of ultra low-power 4-bit CLA in subthreshold regime

摘要

The paper presents the analysis and implementation of ultra low-power, low voltage and low area 4-bit carry look ahead adder circuits. Sub-threshold design technique has been used to reduce the power consumption and area while maintaining low complexity of logic design in the proposed circuit. Simulation results illustrate the superiority of the circuits in sub-threshold region against the conventional low power design technique, in terms of power, area and power delay product (PDP). The CLA is implemented on TSMC 0.18μm process models in Cadence Virtuoso Schematic composer with improved driving ability and circuit robustness at 0.4V single ended supply voltage and simulations are carried out on Spectre S. The proposed 4-bit CLA can operate up to 5 MHz and used 0.035 μW of power and occupied an area of 60×92.5 μm.