A Line TFET design employing Tri-line-gate architecture and U-shaped pockets for minimizing drain field effects

摘要

In this work, using a calibrated 2D TCAD simulation study, we propose and investigate a vertical dual source tri-line-gate (TLG) Tunnel Field-Effect Transistor (TFET) structure with U-shaped n+ pockets. The dual source configuration with U-shaped pockets is sandwiched between three parallel overlapping source-channel vertical line gates. Such a combination minimizes the drain induced barrier thinning effect existing in the conventional L-shaped pocket architecture along with an ON current boosting of ~49% at V_DS=V_GS=0.7V. The resultant I_ON/I_OFF ratio is improved by approximately three orders from ~2×10^{2 to 1.48×105 with a steep subthreshold swing of ~40mV/dec.}