CMOS integrated circuits; Ge-Si alloys; MOSFET; elemental semiconductors; germanium; insulators; passivation; CMOS compatible process; Ge-Sisub1-0.5/subGesub0.5/sub; Si-cap-free passivation; aggressively scaled fin dimension; distance 16 nm; electrostatics; high hole mobility; high-content strained-insulator; size 25 nm; size 3.3 nm; subLG pMOS FinFET; voltage 0.5 V; Electrostatics; FinFETs; Logic gates; Passivation; Silicon; Silicon germanium; Very large scale integration;
机译:<![CDATA [BI
机译:<![CDATA [单PERE超声波喷雾热解介导空心MG
机译:In
机译:高迁移率高Ge含量Si
机译:Bi