A 14b 100MS/s 3.4mm2 145mW 0.18um CMOS Pipeline A/D Converter

机译：14b 100ms / s 3.4mm2 145mw 0.18um cmos管道a / d转换器

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This work proposes a 14b 100MS/s 0.18mum CMOS ADC for the fourth-generation mobile communication systems. The proposed 3-stage pipeline ADC, whose architecture is verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 1

机译：这项工作提出了用于第四代移动通信系统的14b 100ms / s 0.18mum cmos ADC。提出的3阶段管道ADC，其架构通过行为模拟模拟验证，采用宽带低噪声SHA来实现1

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来源
《IEEE Asia Pacific Conference on Circuits and Systems》|2006年||共4页
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Kyung-Hoon Lee; Young-Jae Cho; Hee-Cheol Choi; Yong-Hyun Park; Doo-Hwan Sa; Young-Lok Kim; Seung-Hoon Lee;
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中图分类 TN4-53;
关键词
CMOS integrated circuits; analogue-digital conversion; integrated circuit modelling; low noise amplifiers; sample and hold circuits; wideband amplifiers; 0.18 micron; 1.8 V; 145 mW; 3D fully symmetric layout; A/D converter; CMOS pipeline; ENOB; MDAC; Nyquist input fre;

机译：CMOS集成电路;模拟数字转换;集成电路建模;低噪声放大器;样品和保持电路;宽带放大器;0.18微米;1.8 V;145 MW;3D完全对称布局;CMOS管道;eNOB;MDAC;奈奎斯特输入;

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专利

1. Calibration-free 14b 70MS/s 0.13 μm CMOS pipeline A/D converters based on highmatching 3D symmetric capacitors [J] . K.-H. Lee, H.-C. Choi, K.-J. Moon, Electronics Letters . 2007,第6期

机译：基于高匹配3D对称电容器的免校准14b 70MS / s 0.13μmCMOS流水线A / D转换器
2. Design and simulation of Low Power Successive Approximation Register for A/D Converters using 0.18um CMOS Technology [J] . Kalmeshwar N. Hosur, Girish V. Attimarad, Harish M. Kittur, International Journal of Engineering and Technology . 2016,第2期

机译：采用0.18um CMOS技术的A / D转换器低功耗逐次逼近寄存器的设计和仿真
3. Design and simulation of Low Power Successive Approximation Register for A/D Converters using 0.18um CMOS Technology [J] . Kalmeshwar N. Hosur, Girish V. Attimarad, Harish M. Kittur, International Journal of Engineering and Technology . 2016,第2期

机译：采用0.18um CMOS技术的A / D转换器低功耗逐次逼近寄存器的设计和仿真
4. A 14b 100MS/s 3.4mm2 145mW 0.18um CMOS Pipeline A/D Converter [C] . Kyung-Hoon Lee, Young-Jae Cho, Hee-Cheol Choi, Circuits and Systems, (APCCAS), 2006 IEEE Asia Pacific Conference on . 2006

机译：一个14b 100MS / s 3.4mm2 145mW 0.18um CMOS流水线A / D转换器
5. Design of switched-capacitor and switched-current pipelined analog-to-digital converters in 0.18um CMOS technology. [D] . Dalrymple, Joseph. 2008

机译：采用0.18um CMOS技术的开关电容器和开关电流流水线模数转换器的设计。
6. Modeling and Experimental Demonstration of a Hopfield Network Analog-to-Digital Converter with Hybrid CMOS/Memristor Circuits [O] . Xinjie Guo, Farnood Merrikh-Bayat, Ligang Gao, 2015

机译：具有混合CMOS /忆阻器电路的Hopfield网络模数转换器的建模和实验演示
7. A 12 Bit IF Sampling Pipelined ADC in 0.18um BiCMOS [O] . Liang Li, Dongbing Fu, Mingyuan Xu, 2015

机译：如果在0.18um bicmos中采样流水线ADC，则为12位

A 14b 100MS/s 3.4mm2 145mW 0.18um CMOS Pipeline A/D Converter

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