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FPGA based 1 channel fiber optic analog signal link using 8B/10B encoding scheme

机译:使用8B / 10B编码方案的基于FPGA的1通道光纤模拟信号链路

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The paper presents the details of development of the fiber optic link that will be used to interconnect the various analog signals. Speciality of the link is that the analog signal of frequency up to 1 kHz is transmitted through digital technology. In order to resolve the problem of DC balance and clock/data recovery during the fiber optic data transmission, paper gives a simple and practical solution of 8B/10B encoding and decoding techniques. The paper also gives the solution of clock and data recovery (CDR) by using the 4×-oversampling based digital techniques. The design of 8B/10B encoder has been implemented on transmitter and 8B/10B decoder in receiver module. This solution gives a method of checking scheme and logic operation, through VHDL description language. The proposed circuit is simulated in Xilinx 14.2 ISE tool and implemented on Spartan 3E FPGA. The results obtained from the various tools are presented in this paper. For analog signal link, paper gives the interfacing of analog to digital convertor (ADC) with FPGA in transmitter module and digital to analog convertor (DAC) with FPGA in receiver module.
机译:本文介绍了将用于互连各种模拟信号的光纤链路的开发细节。链接的专业是,通过数字技术传输高达1 kHz的频率的模拟信号。为了解决光纤数据传输期间DC平衡和时钟/数据恢复的问题,纸张提供了8B / 10B编码和解码技术的简单实用的解决方案。本文还通过使用基于4×血页采样的数字技术来提供时钟和数据恢复(CDR)的解决方案。 8B / 10B编码器的设计已经在接收器模块中的发射器和8B / 10B解码器上实现。该解决方案通过VHDL描述语言给出一种检查方案和逻辑操作的方法。所提出的电路在Xilinx 14.2 ISE工具中模拟并在Spartan 3E FPGA上实施。本文提出了从各种工具获得的结果。对于模拟信号链路,纸张为变送器模块中的FPGA和数字转换器(DAC)提供了模拟到数字转换器(ADC)的接口,以及接收器模块中的FPGA。

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