Hardware implementation of a low power SD card controller

摘要

Technical innovation drives the low power consumption requirements in ASIC design. This paper presents a SD card controller, in which two asynchronous units (BIU and CIU) are included for lower power structure. Adding low power mode to finite state machine makes this controller to shut down if no data or command is transferring for a long time. Only one FIFO is used to store temporary data in order to save area, it is still simplified though add some control logics. These modified structures are specifically implemented for low power applications, and hardware cost is reduced at the same time. FPGA prototyping results show the correctness of the proposed design, and it is synthesized by CSMC 180nm CMOS technology process with a clock frequency of 100 MHz, dynamic power consumption of 8.2223mW and 12.2K equivalent logic gates.