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Hardware implementation of KLMS algorithm using FPGA

机译:使用FPGA的KLMS算法的硬件实现

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Fast and accurate machine learning algorithms are needed in many physical applications. However, the learning efficiency is badly subjected to the intensive computation. Knowing that hardware implementation could speed up computation effectively, we use a FPGA hardware platform to implement an on-line kernel learning algorithm, namely the kernel least mean square (KLMS) which adopts the simple survival kernel as the Mercer kernel. By using an on-line quantization method and pipeline technology, the requirement of hardware resources and computation burden can be reduced significantly and the data processing speed can be accelerated apparently without losing accuracy. Finally, a 128-way parallel FPGA platform which works at 200MHz is implemented. It could achieve an average speedup of 6553 versus Matlab running on a 3GHz Intel(R) Core(TM) i5-2320 CPU.
机译:在许多物理应用中,需要快速而准确的机器学习算法。但是,学习效率严重受到密集计算的影响。知道硬件实现可以有效地加快计算速度,我们使用FPGA硬件平台来实现在线内核学习算法,即采用简单生存内核作为Mercer内核的内核最小均方(KLMS)。通过使用在线量化方法和流水线技术,可以大大降低对硬件资源的需求和计算负担,并且可以在不损失准确性的情况下明显地加快数据处理速度。最后,实现了工作在200MHz的128路并行FPGA平台。与运行在3GHzIntel®CoreTM i5-2320 CPU上的Matlab相比,它可以实现6553的平均提速。

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