Reliable Multicore Processors for NASA Space Missions

摘要

The current trend in commercial processors of moving to many cores (30 to 100 and beyond) on a single die poses both an opportunity and a challenge for space based processing. The opportunity is to leverage this trend for space application and thus provide an order of magnitude increase in onboard processing capability. The challenge is to provide the requisite reliability in an extremely challenging environment. In this paper, we will discuss the requirements for reliable space based multicore computing and approaches being explored to deliver this capability within NASA's extremely tight power, mass, and cost constraints. Topics include: i) discussing the salient issues in achieving fault tolerance in a many-core chip, ii) describing the architecture of an existing commercial many-core processor (Tilera Tile64), iii) using it for an examination of the design issues needed for increasing levels of reliability, and iv) a discussion of how the Tile64 is being adapted for space as the Maestro processor and of the tradeoffs involved in making it a practical space design. The OPERA Maestro processor based on the Tilera TILE64 architecture shows potential to give high processing performance at an error rate equivalent to current space deployed uniprocessor systems. We will discuss potential enhancements to the Maestro processor to address NASA specific performance and reliability requirements.