The simulation study of a system of Double Sided silicon microStrip Detectors (DSSDs) and thin multi-line readout cables is being reported. The application is the Silicon Tracking System (STS) of the fixed-target heavy-ion experiment Compressed Baryonic Matter (CBM) [1], under design at the forthcoming accelerator centre FAIR in Germany. A highly segmented low-mass tracking system for the charged particles is the central CBM detector system to resolve the high tracking densities originating from the impact of a heavy-ion beam on the nuclear target. The material budget shall be minimized by utilizing double-sided silicon microstrip detectors in several planar tracking stations, and by arranging the readout electronics at the periphery of the stations. Low-mass multi-line cables shall bridge the distance between the microstrip detectors and the signal processing electronics. The neutron fluence is expected to reach 2x10~(13) n_(eq)cm~(-2) per year for the five years of the expected CBM run which puts us in the regime of LHC, high energy physics experiments. However our task is much more challenging since we use DSSDs, hence both detector sides should be operating at such high fluences. In order to investigate the life time of DSSDs, it is imperative to extract Charge Collection Efficiency (CCE) as a function of fluence for which one has to understand strip isolation in particular on the ohmic side. Hence various isolation techniques have been explored, for example P-stop, P-Spray, modulated P-spray (conventional techniques) and also a new isolation technique (Schottky barrier). The evaluation of the signal transmission in the cables has been performed with the finite element method (FEM) simulation tool RAPHAEL. Based on the performance of the front-end electronics used for early prototyping in the CBM experiment, capacitive and resistive noise contributions from the DSSDs and the readout cables have been extracted.
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