A voltage base electrothermal model for the interconnection and E-Fuse under the DC and pulse stresses

摘要

A DC and pulse stress electro-thermal model that can well describe the dynamic thermal behaviors of most interconnections fabricated in CMOS technology is derived and demonstrated. This model provides for the first time a simple methodology to evaluate the time dependent temperature and resistance of the interconnection under an applied voltage stress, especially critical to E-Fuse development.