This paper presents the design and performance of a phase-locked-loop (PLL) clock synthesizer for low-jitter clock synthesizer applications. This product operates in the range of 100 MHz to 700 MHz with very low phase noise and low-voltage-differential-signal (LVDS) outputs. The design focuses on the minimization of the phase noise, or timing jitter, of the PLL. Reduction of phase noise is achieved with proper choice of PLL circuit architecture, optimization of PLL loop parameters, careful design of the voltage-controlled-oscillator (VCO), cognizant matching of the charge pump currents, and careful physical layout design throughout. This novel PLL design does not require external components for operation that are typically required for load capacitors of the crystal oscillator. Additionally, the high-frequency LVDS outputs are compliant with the TIA/EIA-644 specification (IEEE Std 1596.3-1996). Clock generation is obtained with the use of a fundamental crystal in the range of 5-27 MHz or an external applied clock operating in the same frequency range. Within the PLL architecture is an internal RC filter that helps to determine the dynamic performance of the loop. Power is applied to a single VDD supply pin with operation in the range 3V-5V and capable of functioning down to 2.7V. The LVDS outputs produce a 400mV signal swing on a 1.2V common mode level under 50驴 load. The output common-mode level is maintained internally with common-mode-feedback (CMFB). This PLL design utilizes a 0.5-驴m N-well CMOS process technology. The active die area is 1.6 mm2.
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