Power supply induced clock jitter accumulation is a function of several variables including the power supply rejection characteristics of circuits in the signal path, signal path electrical length, signaling frequency, and voltage supply noise magnitude and frequency. Brute force, closed-loop, transistor-level modeling and simulation of clock timing in the presence of an extracted power delivery network are resource intensive. In addition, circuit and power delivery network designs are often not complete enough to run such analyses at an early stage in the design cycle, and the longer a design waits to identify circuit and supply sensitivities, the more costly the corrections become. Understanding the relationships between the signal path electrical length, signaling frequency and supply noise frequency enables early jitter estimation and can be used to drive both circuit and power delivery network design optimization. This paper summarizes the general inter-dependencies between these variables and then demonstrates how these principles might be used to make design optimizations in the context of the Low Power Double Data Rate Four (LPDDR4) interface.
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