An efficient hardware based MAC design in digital filters with complex numbers

摘要

This paper proposes a novel fixed point complex number multiply accumulate circuit, which is used in real time digital signal processing applications. The proposed architecture consists of multiplier-cum-accumulator which can be used as multiplier as well as MAC. Here the previous MAC result is added as one of the partial products of the current multiplication. So the depth of the multiplier-cum-accumulator unit remains same as O(log2 n) in case of Wallace tree multiplier based multiplier-cum-accumulator and O(n) in case of Braun multiplier based multiplier-cum-accumulator. And hence the separate accumulator with depth O(log2 n) can be avoided. The performance results are showing that proposed architecture gives the better performance compared with conventional fixed point complex number MAC. The proposed architecture achieves an improvement factor of 32.4% in Wallace tree and 19.1% in Braun multiplier based fixed point complex number MAC with out pipeline using 45 nm technology library. The same architecture achieves an improvement factor of 14.6% in Wallace tree and 12.2% in Braun multiplier based fixed point complex number MAC with pipeline.