We presented a communications-inspired circuit-level technique that can take advantage of the error tolerance of the overlying applications to reduce power dissipation, and an architecture technique that takes advantage of the spatial and temporal variations in NoC bandwidth requirements to reduce power dissipation. We believe that such an integrated approach, where we explore the opportunities for improving the energy efficiency at each level in the design hierarchy based on the constraints/specifications at other levels in the hierarchy, needs to be adopted to design highly energy-efficient VLSI systems.
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