The FPGA implement of ADPLL without retimed clock

摘要

A modified method to evaluate the phase of all digital phase-locked loop (ADPLL) output signal is proposed in this paper for improving the robustness property of the loop. The reference clock is used throughout the system as the synchronous clock, which can avoid the metastable output and the injection spurs caused by retiming mechanism, and differential units are added to reduce the accumulation of phase error. Besides, a time-digital converter (TDC) based loop shifting flip-flops is proposed to achieve a wide range of operation. The FPGA simulation results show that the error of frequency detector is less than 0.2‰, and the loop get into locking by 12 µs and stable in the condition of FSW=4.8.