This talk will highlight how we are eager to embrace phenomena that were considered catastrophic reliability concerns until recently, and “optimize” them to create memory cells for potential replacement of conventional NAND, NOR and DRAM cells. If you cannot fight them, join them! Few examples are (a) defect percolation-path induced dielectric breakdown — conductive bridge filamentary cells in RRAM; (b) device snapback — capacitor-less DRAM thyristor memory cells (TRAM); (c) e-p generation/impact ionization — floating body capacitor-less DRAM (FBE); (d)localizedhigh-current, joule heating — phase change memory; (e) oxygen vacancy migration-metal oxide/CMO RRAM. There are several challenges in working with and optimizing phenomena that are generally considered chaotic and random in nature. This talk will discuss practical issues like noise — RTS, drift in retention, stuck bits, error correction needs etc. in emerging memory technologies.
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