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Record-high 121/62 #x03BC;A/#x03BC;m on-currents 3D stacked epi-like Si FETs with and without metal back gate

机译:具有和不具有金属背栅的创纪录高121/62μA/μm导通电流3D堆叠Epi状Si FET

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摘要

A sequential layered integration technology that can fabricate 3D stackable epi-like Si FETs with and without metal back gate (MBG) under sub-400°C are proposed in this article. With laser crystallized epi-like Si and CMP thinning processes for channel fabrication, 3D stackable ultra thin body (UTB) n/p-MOSFETs with low-subthreshold swings (88 and 121 mV/dec.) and high on-currents (121 and 62 μA/μm) are demonstrated. With additional metal back gate structure, UTB devices can be desirably operated in a positive or negative threshold voltage range with γ values of 0.51 (n-MOSFETs) and 0.56 (p-MOSFETs) for favoring its applications in 3D logic circuits. In addition, such thin and high quality channel and metal back gate scheme is not only promising for conventional p-n junction device but also junctionless (JL) scheme, which can simplify the fabrication and achieve further scaling.
机译:本文提出了一种顺序分层集成技术,该技术可以在低于400°C的温度下制造带有和不带有金属背栅(MBG)的3D可堆叠Epi式Si FET。借助激光晶化的磊晶状Si和CMP减薄工艺进行沟道制造,可实现3D可堆叠超薄体(UTB)n / p MOSFET,具有低亚阈值摆幅(88和121 mV / dec。)和高导通电流(121 and展示了62μA/μm)。借助额外的金属背栅结构,UTB器件可以理想地在正或负阈值电压范围内工作,其γ值为0.51(n-MOSFET)和0.56(p-MOSFET),从而有利于其在3D逻辑电路中的应用。另外,这种薄且高质量的沟道和金属背栅方案不仅对于常规的p-n结器件是有希望的,而且对于无结(JL)方案是有希望的,其可以简化制造并实现进一步的缩放。

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