Since the end of 2008, the first FPGAs based on asynchronous logic cells are commercially available. Although the internal logic of the FPGA fabric is based on pure asynchronous logic, the design style for asynchronous FPGAs does not differ from that of classical FPGAs. The design for asynchronous FPGAs can be synthesized in the same way as for synchronous FPAGs from register transfer level based on standard hardware description languages like VHDL or Verilog. The fundamental advantage of these asynchronous FPGAs is that the intrinsic speed of the FPGA fabric is much higher at about 1.5 GHz compared to a few hundred MHz for traditional FPGAs. In this paper, it is examined whether this speed advantage on the physical level translates to advantages on the design level for high performance DSP applications.
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