Optimization of Modular Multiplication on FPGA Using Don't Care Conditions

摘要

In this paper we make use of don't care conditions to propose a word-level Don't-Care Optimization (DC-Opt) technique for modular multipliers by taking into account LUT-based FPGA architectures. This technique can easily be utilized for large arithmetic circuits and it can provide a superior implementation in terms of area compared to the state-of-the art optimizations. Experimental results show an average saving of 17% of area consumption compared to the conventional binary structures and Residue Number System (RNS) based multipliers on FPGA.