Revisiting FPGA Routing under Varying Operating Conditions

摘要

FPGA devices are continually integrating more and more resources to satisfy emerging applications' performance requirements, which has increased the power of cutting-edge devices beyond CPUs. Consequently, more aggressive power reduction techniques have been explored recently, including voltage scaling, which is also adopted by several commercial FPGA families. In this paper, we investigate the FPGA routing (both the interconnection network and the routing algorithm) under variable voltage, temperature, as well as degradation. We first examine routing switch boxes (SBs) and point out that SBs with different wire segment lengths have different sensitivity/tolerance to varying operating conditions. Accordingly, we show how architectures with similar overall efficiency in the nominal condition can have a different performance at the scaled voltage or temperature. Finally, we reveal that unlike current FPGA flow that first accomplishes the placement and routing and ex-posts multi-condition timing analysis, bringing the timing information of the actual operating condition in the placement and routing steps helps the underlying algorithms to utilize the resources that have better relative efficiency in the target condition, leading to higher performance.