Hardware Implementations with High Throughput, Low-Latency and Low-Area for Matrix Inversion

摘要

This paper proposes two hardware architectures for matrix inversion, through the use of single and double-precision floating-point representations. The architectures use a modified version of the Gauss-Jordan algorithm that accelerates the processing of matrix inversion. The modified algorithm starts performing the normalization and elimination steps from the column that follows the pivot column instead of the first matrix column, which speeds up the process of the matrix inversion and hence achieves high performance. The first of the two hardware architectures is purely designed with registers, while memory blocks are required in the second architecture. The implementation results show that the modified version of the Gauss-Jordan algorithm has considerably improved the hardware performance of the matrix inversion, in terms of latency, throughput and hardware resources. The architectures have been optimized for Xilinx FPGAs and they are capable of operating at frequencies of 211.999 and 422.654 MHz in a Zynq xc7z045 FPGA.