Disclosed in embodiments of the present invention is a parallel hardware architecture for floating point matrix inversion, for use in resolving the problem of fixed matrix dimensions when an existing matrix operation is implemented by hardware. The parallel hardware architecture for floating point matrix inversion in the embodiments of the present invention comprises: a matrix writing module, used for writing matrix data of an augmented matrix in a first memory and a second memory, the first memory and the second memory dynamically allocating storage spaces to the matrix data; an initial pivot positioning module, used for positioning an initial pivot row of the augmented matrix; a row switching module, used for switching the first row of the augmented matrix with the pivot row; a row elimination module, used for carrying out normalization and row elimination calculation, and positioning a next pivot row; and a triggering module, used for repeatedly and alternately triggering the row switching module and the row elimination module, and outputting the matrix data in the second memory until when the matrix to be inverted stored in the first memory becomes a unit matrix. The embodiments of the present invention also provide a parallel computing method for floating point matrix inversion.
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